1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor device having a redundant scheme.
2. Description of the Prior Art
Generally in a non-volatile semiconductor memory device, an avalanche phenomenon is caused by applying an inverse bias voltage across a PN-junction in a semiconductor substrate, high energy carriers generated by the avalanche phenomenon are accumulated in a floating gate, and thereby information is stored. On the other hand, in order to rewrite the information, after the accumulated carriers have been discharged by irradiating ultra-violet rays or the like or by applying an inverse electric field, writing of information is effected. However, while such rewriting of information is repeated many times, characteristics of a memory element would be deteriorated, and poor holding of data would arise.
Also, in a single-transistor type of dynamic (volatile) semiconductor memory device which employs a capacitor as data storage means, there exists a problem of soft errors. Namely, due to the fact that electric charge stored in a capacitor would be reduced by .alpha.-rays or the like, data held thereby would be inverted, resulting in malfunctions. In order to prevent such lowering of reliability of held information, counter-measure is taken such that parity bits consisting of 4 bits are added to one bite of information, or that all the bits are stored respectively in a plurality of memory elements and a true value is determined by majority decision technique for the information stored in these plurality of memory elements.
However, in the prior art, in the case of determining a true value by majority decision technique, since each bit is stored in a fixed number of memory elements regardless of times of writing and erasing of information, it has been compelled to determine the above-mentioned fixed number on the assumption of the mode of use in which the times of writing and erasing is the highest, and therefore, there has been a problem that an amount of information that can be stored in a single semiconductor memory device has been limited.
Furthermore, there has been a problem that if times of writing and erasing becomes large, since a probability of generating poor data holding in a memory element becomes high, even though the same data bit is held in a fixed number of memory elements, these occurs a difference in reliability of information depending upon a difference in the times of writing and erasing, resulting in difficulty to deal with the information for processing.